Electronic Warfare Staff October 20, 2021
Michael Lu, Stefan Gianordoli, Tobias Kupka, Gunnar Armbrecht and Stephan Kunz said that automotive wiring interconnections must be defined to help transform PCIe from an internal electronic control unit interface to an internal ECU interface.
PCIe (Peripheral Component Interconnect Express) continues to be popular in the automotive industry to meet the critical high-bandwidth and low-latency computing requirements of distributed automotive architectures, but the challenges of its widespread adoption still exist. In order for automotive processors to take full advantage of this interface standard for shared processing, automotive wiring interconnections must be defined to help convert PCIe from an interface within an electronic control unit (ECU) to an interface between ECUs.
Implementing native PCIe through automotive cable channels (ie, a combination of automotive cables and connectors) requires careful consideration of physical interconnections. Electronics companies TI, Rosenberger, and the GG Group have proposed PCIe specifications for the automotive cable channels of vehicles, defining PCIe on the cable channels.
Original equipment manufacturers and Tier 1 suppliers are rethinking the architecture of the automotive data backbone to support advancements in advanced driver assistance systems (ADAS) and vehicle connectivity.
The data backbone no longer relies on calculations based on domains (such as ADAS domains), but transforms from domains to regional architectures, and combines local computing nodes or regional controllers to connect ECUs and interfaces according to their internal locations. Regions, regardless of their respective domains (Figure 1). These regional controllers then connect to a powerful central computing node and process the data accordingly.
In order to realize distributed processing in the regional architecture, the automobile data backbone network must adopt high-speed interfaces that support high bandwidth and low latency. In particular, when sharing data for safety-critical real-time processing, low latency must be considered. The PCIe ecosystem has addressed these high-bandwidth, low-latency performance requirements of industrial data centers.
Implementing PCIe through automotive channels requires careful consideration of the entire physical interconnection. The complete end-to-end channel (transmit-receive or Tx-to-Rx) link consists of two PCB channels located at both ends of the car cable channel.
Each PCB channel includes the part from the Tx/Rx PHY to the corresponding PCB connector. Automotive cable channels can consist of a single cable assembly, such as a bulk cable with two assembled connectors, or multiple cable assemblies. In the case of multiple cable assemblies, the cable channel includes inline connections. According to the channel limitation on the required bandwidth, the cable channel length limitation depends on the high-speed characteristics, such as insertion and return loss.
While meeting original equipment manufacturers' needs for universal cable channel solutions and minimizing cable cost and weight, some trade-offs need to be made to maintain the advantages of native PCIe.
One suggestion is to keep the cable channel type similar to other high-speed interfaces. The cable assembly used for PCIe should be as similar as possible to other high-speed interface technologies, such as 2.5/5/10GBASE-T1 Ethernet. In this way, the original equipment manufacturer only needs to verify a single connector interface and cable type combination for the various high-speed interfaces of the entire vehicle.
In order to reduce the number and weight of cables, only the necessary high-speed in-band PCIe signals need to be connected through the car cable, and the low-speed sideband signals on the local PCB may remain unconnected. To reduce the risk of electromagnetic interference (EMI) resonance, the 100MHz PCIe reference clock may be omitted from the cable interconnection. The PCIe specification supports separate reference non-extensions and separate reference independent extensions for independent clocks on either side of the cable.
Native PCIe transmission requires dedicated Tx and Rx channels, which means that each channel requires two shielded twisted pair (STP) cables (one Tx, one Rx) to interface with other high-speed interfaces (such as multi-Gigabit Ethernet. Needed) Note that this trade-off in the number of cables preserves the native PCIe performance and the non-proprietary PHY interface on the cable.
In order to maintain similar PHY layer requirements, native PCIe implements non-return-to-zero (NRZ) signaling with dedicated Tx and Rx directions, and can pass electromagnetic compatibility (EMC) requirements. Compared with PAM-4 or PAM-16 modulation schemes, NRZ signaling maximizes the vertical eye pattern margin. Using dedicated Tx and Rx channels, there is no need to implement a separate automotive PCIe PHY to support a full-duplex, two-way signaling interface, which requires a complex digital signal processor to eliminate noise and echo.
It is important to determine the PHY speed requirements of the links between connections and align them with the performance that cables and connectors can provide. The channel specification is needed to test the high-speed channel parameters against these limits. The channel specification describes the cable and PCB channel requirements based on S-parameters.
The key parameter is the required frequency bandwidth, mainly insertion loss and return loss. Considering EMC behavior, it is useful to specify shielding and coupling attenuation. A detailed description of the measurement settings and procedures is also necessary to compare the results.
The proposed automotive PCIe channel specification and measurement setup and procedure description can serve as the basis for possible official PCI-SIG standardization for automotive use cases.
The cable channel must support insertion loss without suction, drop or notch, and the Nyquist frequency of the highest transmission rate is at least 10% higher to ensure a safety margin across temperature, aging, and manufacturing processes. Table 1 shows the recommended cable limits.
Automotive certification requires different aging tests, such as long-term aging at high temperatures for 3,000 hours, to characterize the stability of cable performance. After all aging tests, it is expected that the pre-defined critical high frequency limit will be maintained. Different cable design parameters must also be considered, such as strand length, core dielectric constant, and isolation material selection to meet interface performance requirements.
The GG 2Speed 251 STP cable may be an automotive cable suitable for PCIe 3.0. The shielding layer consists of aluminum-plastic foil wrapped on two twisted cores (Figure 2). The copper braid is an additional shield to help meet the required EMC performance (shielding and coupling attenuation) up to 4.4GHz.
The cable can reach up to 5.0GHz. Due to the cable structure, a gap is displayed near 5.2GHz. The gap is mainly affected by the twist distance of the white and green lines. Using the following formula, the cable also shows good performance against the proposed automotive PCIe 3.0 original cable limitations:
IL [dB/10m] = – (0.69f0.45 0.0027f)/15 where • f = frequency up to 4400 MHz.
Cables that support higher frequencies are under development; the 2Speed 256 prototype meets the increased frequency requirements of PCIe 4.0, and its bandwidth can support up to 10GHz linear insertion loss.
Rosenberger provides high-speed modular twisted pair data (H-MTD) connectors for differential signal transmission and heavy frequency modulation (HFM) in case coaxial transmission is preferred. Both systems provide 360° shielding.
Since the return loss is mainly determined by the connector, the impedance along the H-MTD and HFM are accurately matched with the reference impedance of 100Ω and 50Ω, respectively.
The redriver and retimer recover and offset the additional insertion loss and signal-to-noise ratio degradation that naturally occurs when PCIe is transmitted over lossy media. Since PCIe 2.0, the redriver has been part of the PCI-SIG integrator's approved component list. At the same time, since PCIe 4.0, the retimer has officially become a part of the PCIe Base specification.
Table 2 shows the comparison between the redriver and the retimer. For internal ECU and short cable applications, linear redrivers are suitable. For native PCIe 3.0 transmission, TI redrivers use 2Speed 251 STP cables through the Rosenberger H-MTD connector system for applications up to 5m.
For longer cable distance applications, the retimer can maximize the signal margin. Compared with redrivers, PCIe retimers provide more complex functions, including adaptive equalizers, decision feedback equalization, and shunt rules. The retimer also provides a variety of link monitoring diagnostic functions to assist system-level functional safety, including Rx link margin, internal eye diagram monitoring, and cable fault detection. For native PCIe 3.0 transmission, TI stated that its retimer is for applications up to 10m using a 2Speed 251 STP cable through the H-MTD connector system.
The following assumptions are used to estimate the maximum target cable length: * PCIe specification insertion loss Rx is limited to PCIe 3.0: 22dB at 4.0GHz * At 4.0GHz, assuming the following insertion loss (IL) characteristics in the link channel * ILcable_m = 2Speed 251 STP cable : 2.75dB/m * ILPCB = FR4 PCB trace: 6” (152.4mm) is 4dB * ILconn = connector and additional PCB components: 1.5dB * estimated maximum cable length (m) = (ILtotal – 2xILPCB-2xILconn) / ILcable_m
PCIe is an attractive interface that can meet the critical high-bandwidth and low-latency computing requirements of next-generation distributed automotive architectures. In order for the processor to make full use of the PCIe interface for shared processing, automotive wiring interconnections are required to implement local PCIe transmission through the automotive cable channel. In this way, the physical layer design will clear the way for automotive processors to realize their complete computing, efficiency, and connectivity potential.
Parameter/measurement recommended limit bandwidth 4.4GHz (1) Insertion loss budget 26.4dB@4GHzz Return loss budget 6dB@4GHz Shielding/coupling attenuation 45dB@4GHz /55.5dB@4GHz
PCIe linear re-driver PCIe retimer Low-power solution (no heat sink required) High-power solution (heat sink required in most cases) Ultra-low latency (100ps) Medium latency (based on PCIe 4.0 specification less than or equal to 64ns requirements) Does not participate in the chain Route training, but transparent to the negotiation between the root complex and endpoints (protocol agnostic) Fully participate in the link training between the root complex and endpoints (protocol awareness) No 100MHz reference clock is required, 100MHz reference clock is needed to help with insertion loss Helps reduce insertion loss, jitter, crosstalk, reflection, and channel-to-channel skew CTLE is a typical equalization circuit CTLE, DFE and transmitter FIR is a typical equalization circuit used. The total solution cost is ~X total solution cost is ~( 1.3X -1.5X)
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